verilog.v 274 B

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  1. always @(negedge reset or posedge clk) begin
  2. if (reset == 0) begin
  3. d_out <= 16'h0000;
  4. d_out_mem[resetcount] <= d_out;
  5. laststoredvalue <= d_out;
  6. end else begin
  7. d_out <= d_out + 1'b1;
  8. end
  9. end
  10. always @(bufreadaddr)
  11. bufreadval = d_out_mem[bufreadaddr];