vhdl.vhd 830 B

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  1. library IEEE
  2. user IEEE.std_logic_1164.all;
  3. use IEEE.numeric_std.all;
  4. entity COUNT16 is
  5. port (
  6. cOut :out std_logic_vector(15 downto 0); -- counter output
  7. clkEn :in std_logic; -- count enable
  8. clk :in std_logic; -- clock input
  9. rst :in std_logic -- reset input
  10. );
  11. end entity;
  12. architecture count_rtl of COUNT16 is
  13. signal count :std_logic_vector (15 downto 0);
  14. begin
  15. process (clk, rst) begin
  16. if(rst = '1') then
  17. count <= (others=>'0');
  18. elsif(rising_edge(clk)) then
  19. if(clkEn = '1') then
  20. count <= count + 1;
  21. end if;
  22. end if;
  23. end process;
  24. cOut <= count;
  25. end architecture;